In recent years, in the trend to the progress of the miniaturization of DRAM, there is such a tendency that the capacitor area is narrowed and the capacitor capacitance is reduced. Therefore, in order to increase the capacitor capacitance, the approach to increase the height of the capacitor is employed.
In this case, in the case that the capacitor is formed three-dimensionally on the silicon substrate like the stacked cell, the height of the contact hole formed in the interlayer insulating film is extremely raised if it is tried to connect the upper wiring to the gate electrode and the source/drain regions that are formed in the peripheral circuit portion.
Then, as the height of the contact hole is increased, there is the possibility that the fine patterning by the dry etching becomes difficult or the contact resistance is increased because the coverage of the conductive film that is formed in the contact hole becomes bad.
Therefore, recently such problem is settled not by forming the contacts between the upper and lower conductive patterns at a time but by employing the two-stage contact stacked structure consisting of the upper contact and the lower contact.
Next, the contact structure in the DRAM in the prior art will be explained with reference to FIGS. 1(a),(b) and FIG. 2 hereunder.
FIG. 1(a) shows the state after the bit line is formed on the interlayer insulating film that covers the MOS transistors in the memory cell portion.
In FIG. 1(a), in the active regions, which are surrounded by the element isolation insulating film 104, of the memory cell portion 102 and the peripheral circuit portion 103 on the silicon substrate 101, a plurality of gate electrodes 106, 107 are formed on the silicon substrate 101 via the gate oxide films 105a, 105b respectively. Also, the protection insulating film 108 made of the silicon nitride film is formed on the gate electrodes 106, 107.
The impurity diffusion layers 106a, 106b are formed in the silicon substrate 101 on both sides of the gate electrodes 106 in the memory cell portion 102. Then, the MOSFETs are constructed by the impurity diffusion layers 106a, 106b, the gate electrodes 106, etc.
Also, as shown in a plan view of FIG. 3, in the memory cell portion 102, a plurality of gate electrodes 106 are formed on one active region 110 surrounded by the element isolation insulating film 104, and the impurity diffusion layers 106a, 106b are formed between a plurality of gate electrodes 106 respectively. In this case, the gate electrodes 106 constitute a part of the word line.
FIG. 3 shows positions of the bit line contact and the storage contacts in one memory cell portion 102. In this case, FIG. 1(a) shows a sectional shape viewed from a I—I line in FIG. 3.
In contrast, in the peripheral circuit portion 103, the sidewalls 107s made of the silicon nitride, for example, are formed on the side surfaces of the gate electrode 107 and the impurity diffusion layers 107a, 107b having the LDD structure are formed in the silicon substrate 101 on both sides of the gate electrode 107. The MOSFET is constructed by the gate electrode 107, the impurity diffusion layers 107a, 107b, etc.
In this case, the sidewalls 106s made of the silicon nitride, for example, are also formed on the side surfaces of the gate electrodes 106 in the memory cell portion 102.
The MOSFETs having the above structure and the silicon substrate 101 are covered with the first interlayer insulating film 109 made of BPSG. Also, in the memory cell portion 102, the lower contact holes 109a, 109b are formed in the first interlayer insulating film 109 at the positions that are sandwiched between the gate electrodes 106.
These lower contact holes 109a, 109b are the self-align contacts that are positioned between the gate electrodes 106 in a self-alignment manner.
The lower plugs 110a, 110b made of the doped silicon are formed in the lower contact holes 109a, 109b. 
In addition, the second interlayer insulating film 111 made of BPSG is formed on the lower plugs 110a, 110b and the first interlayer insulating film 109.
The upper contact hole 111a is formed in the second interlayer insulating film 111 on the lower plug 110a for the bit line contact in the memory cell portion 102. Also, the lower contact holes 111b, 111c having a depth to reach the impurity diffusion layers 107a, 107b respectively are formed in the first and second interlayer insulating film 109, 111 in the peripheral circuit portion 103.
The upper plug 112a made of the metal film having the multi-layered structure is formed in the upper contact hole 111a for the bit line in the memory cell portion 102. Also, the lower plugs 112b, 112c made of the metal film having the multi-layered structure are formed in the lower contact holes 111b, 111c in the peripheral circuit portion 103.
In addition, in the memory cell portion 102, the bit line 113 connected to the upper plug 112a is formed on the second interlayer insulating film 111. The upper surface of the bit line 113 is covered with the silicon nitride film 115, and the sidewalls 116 made of the silicon nitride are formed on the side surfaces of the bit line 113.
Then, as shown in FIG. 1(b), the steps of forming the upper plugs for the storage contact in the memory cell portion 102 is carried out.
In FIG. 1(b), the third interlayer insulating film 117 made of BPSG, or the like is formed on the bit line 113 and the second interlayer insulating film 111. Then, the upper contact holes 117b connected to the lower plugs 110b for the storage contact are formed on the third interlayer insulating film 117 in the memory cell portion 102. The upper plugs 118 made of the doped silicon are formed in the upper contact holes 117b. 
In this case, a sectional shape that is viewed from a III—III line in FIG. 1(b) and a II—II line in FIG. 3 is shown in FIG. 4.
Then, as shown in FIG. 2, the capacitors 120 are formed on the third interlayer insulating film 117 in the memory cell portion 102. Then, the fourth interlayer insulating film 121 for covering the capacitors 120 is formed on the third interlayer insulating film 117. Also, the upper plugs 122b, 122c connected to the lower plugs 112b, 112c are formed in the third and fourth interlayer insulating films 117, 121 in the peripheral circuit portion 103.
In the peripheral circuit portion 103, the lower plugs 112b, 112c and the upper plugs 122b, 122c are formed by the metal film having the triple-layered structure consisting of titanium (T), titanium nitride (TiN), and tungsten (W) respectively. The titanium is formed to lower the contact resistance of the metal film. Also, the titanium nitride is formed as the barrier metal to prevent the increase of the resistance caused by the reaction between the tungsten and the titanium.
Next, the capacitors are formed by following steps.
First, the silicon nitride film 119 is formed on the third interlayer insulating films 117, then the BPSG film (not shown) is formed thick on the silicon nitride film 119, and then the openings each having the capacitor shape are formed on the upper plugs 118 and their peripheral areas in the memory cell portion 102 by patterning the BPSG film and the silicon nitride film 119 in the memory cell portion 102. Then, the silicon film is formed along the upper surface of the BPSG film and the inner surfaces of the openings, and then the silicon film on the BPSG film is removed by the chemical mechanical polishing (CMP) method. Then, if the BPSG film is removed by the hydrofluoric acid, the cylindrical silicon films are left on the third interlayer insulating films 117. These silicon films are used as the storage electrode 120a of the capacitor 120 respectively. In this case, the silicon nitride film 119 acts as the etching stopper in removing the BPSG film.
The dielectric film 120b is formed on the surface of the storage electrode 120a. Then, the cell plate electrode 120c is formed on the dielectric film 120b. 
The cell plate electrode 120c, the dielectric film 120b, and the silicon nitride film 119 are removed from the peripheral circuit portion 103 by the patterning.
Then, after the capacitors 120 are formed, the fourth interlayer insulating film 121 is formed.
In the peripheral circuit portion 103, the third and fourth interlayer insulating films 117, 121 are patterned and thus the upper contact holes 121b, 121c are formed on the lower plugs 112b, 112c. Subsequently, the upper plugs 122b, 122c made of the same multi-layered structure as the lower plugs 112b, 112c are formed in the upper contact holes 121b, 121c. 
The upper wirings 123b, 123c formed on the fourth interlayer insulating film 121 in the peripheral circuit portion 103 are connected to the impurity diffusion layers 107a, 107b via the upper plugs 122b, 122c and the lower plugs 112b, 112c. 
Meanwhile, in the peripheral circuit portion 103 of the semiconductor device as described above, the upper wirings 123b, 123c are connected electrically to the impurity diffusion layers 107a, 107b via the upper plugs 122b, 122c and the lower plugs 112b, 112c, which are stacked in two stages. In this case, if the upper contact holes 121b, 121c are displaced, there is such a possibility that, as shown in FIG. 5, the upper plugs 122b, 122c are dropped lower than the upper surfaces of the lower plugs 112b, 112c. 
The reason for that the upper plugs 122b, 122c are dropped deeper than the upper surfaces of the lower plugs 112b, 112c in this manner is that, when the upper contact holes 121b, 121c are formed, the over-etching is applied to assure the openings without the problem irrespective of the variation in the film thickness of the third and fourth interlayer insulating film 117, 121.
A portion A in FIG. 5 shows the state that a part of the upper contact hole 121c protrudes from the lower plug 112c to reach the neighborhood of the gate electrode 107. In this state, it is possible that the breakdown voltage between the lower plug 112c and the gate electrode 107 is lowered. Also, if the gate electrode 107 has the salicide structure and the protection insulating film 108 is not present thereon, there is a possibility that the lower plug 112c and the gate electrode 107 are short-circuited.
A portion B in FIG. 5 shows the case that a part of the upper contact hole 121b is deviated from the lower plug 112b to reach the element isolation insulating film 104. There is such a possibility that, when the upper contact hole 121b is formed, the edge of the element isolation insulating film 104 is etched to expose the silicon substrate 101 around the impurity diffusion layer 107a. Then, when the upper plug 122b is connected on the impurity diffusion layer 107a and its periphery on the silicon substrate 101, the junction leakage is increased.
Also, a portion C in FIG. 5 shows the upper surface of the lower plug 112b and its peripheral portion when a part of the upper contact hole 121b protrudes from the lower plug 112b. Since the upper contact hole 121b formed on the side of the lower plug 112b has the high aspect ratio, the coverage of the metal film formed in the hole 121b becomes worse. As a result, the titanium nitride that must be formed thin essentially becomes further thin locally. Thus, it is possible that the tungsten and the titanium react with each other at the location and thus the contact resistance is increased.
In contrast, as shown in FIG. 2, the upper contact holes 117b under the capacitors 120 are shallower than the contact holes 121b, 121c in the peripheral circuit portion 103 by the difference in the film thickness between the fourth interlayer insulating film 121 and the second interlayer insulating film 111. Normally, the fourth interlayer insulating film 121 is formed considerably thicker than the second interlayer insulating film 111. Therefore, an amount of the over-etching, which is applied to compensate the variation in the film thickness when the upper contact holes 117b under the capacitors 120 are formed, becomes smaller than that of the over-etching applied when the upper contact holes 121b, 121c in the peripheral circuit portion 103 are formed. As a result, even if the upper contact holes 117b are deviated from the upper surfaces of the lower plugs 110b because of their displacement, such deviation is hard to become the fatal problem.